1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor, and more particularly, to a method of fabricating a thin film transistor having an LDD region in an active layer.
2. Discussion of the Related Art
Amorphous silicon (a-Si) thin film transistors (TFTs) have been mainly used for a liquid crystal display device. Polysilicon (poly-Si) TFT liquid crystal displays (LCDs), on the other hand, use polysilicon of a relatively high mobility as compared with amorphous silicon and have driving circuits formed on the same display panel instead of on separate driving circuits. The polysilicon TFT contains electrons and holes having higher mobilities than those of the amorphous TFT, and can be designed to embody a CMOS (complementary metal oxide silicon) structure. Therefore, instead of connecting the driving circuit ICs on the substrate, large parts of the driving circuit can be formed of TFTs together with TFTs for a pixel array of the display device. In addition, the polysilicon TFTs can be manufactured on a large-sized glass substrate, since recent development in crystallization techniques using a laser has made it possible to fabricate the polysilicon TFTs at a similar temperature to that for fabricating the amorphous TFTs.
As described above, a liquid crystal display using polysilicon TFTs has both a driving circuit part and a pixel part on the same glass substrate. Such polysilicon TFTs for the driving circuit part (referred to as "circuit TFTs") can perform high speed switching owing to their high performance, but polysilicon TFTs at the pixel array part (referred to as "pixel TFTs") may generate operational problems in the pixel array due to their high drain currents (off-currents) in their off states. To solve this problem, the polysilicon TFTs (especially for the pixel array) employ so-called lightly doped drain (LDD), offset, and/or dual gate structures.
FIGS. 1A-1F are cross-sectional views illustrating a process for fabricating a liquid crystal display having conventional thin film transistors. In each drawing, the left part indicates a pixel TFT and the right part shows circuit TFTs. The circuit TFTs include an n-type circuit TFT and a p-type circuit TFT that are electrically connected to each other to form a CMOS structure.
Referring to FIG. 1A, a polysilicon layer is formed on an insulating substrate 100 and pattern-etched by a photolithographic process to form an active layer 10 for the pixel TFT, an active layer 20 for the n-type circuit TFT, and an active layer 20' for the p-type circuit TFT. In this process, the polysilicon layer is formed by depositing polycrystalline silicon, or by depositing an amorphous silicon layer on the substrate and subsequently crystallizing the amorphous silicon layer.
Next, an insulating layer and a metal layer are sequentially formed on the entire surface of the substrate. The metal layer is then pattern-etched by a photolithographic process to form a gate electrode 12 for the pixel TFT, a gate electrode 22 for the n-type circuit TFT, and a gate electrode 22' for the p-type circuit TFT. The insulating layer is pattern-etched by a photolithographic process using these gate electrodes 12, 22 and 22' as a mask to form a gate insulating layer 11 for the pixel TFT, a gate insulating layer 21 for the n-type circuit TFT, and a gate insulating layer 21' for the p-type circuit TFT. The insulating layer can be formed by depositing an insulating material, such as silicon oxide, silicon nitride, or the like using a plasma enhanced chemical vapor deposition (PECVD) technique. The metal layer can be formed by depositing aluminum or chrome using a sputtering method.
Referring to FIG. 1B, a photoresist is formed on the entire surface of the substrate, and a selective exposure and development process is carried out to form a photoresist pattern PR covering the entire surface of the active layer 20' of the p-type circuit TFT, the gate electrode 12, and a portion of the active layer 10 adjacent to the gate electrode 12 at the pixel TFT.
Impurity-doping using n.sup.+ -type impurities is then performed on the resultant structure to form source and drain regions 10S and 10D in the active layer 10 of the pixel TFT, and source and drain regions 20S and 20D in the active layer 20 of the n-type circuit TFT. Conventionally, n.sup.+ -type impurities (impurities for forming n.sup.+ semiconductor regions) of about 10.sup.19-21 /cm.sup.3 are doped in this process. The photoresist patterns PR formed over the active layers 10 and 20 function as a mask for blocking the n.sup.+ -type impurities. As a result, portions of the active layer 10 of the pixel TFT between channel region 10C and the source and drain regions 10S and 10D remain undoped. In the active layer 20 for the n-type circuit TFT having no photoresist thereon, the source and drain regions 20S and 20D are formed in contact with the right and left sides of the channel region 20C.
Referring to FIG. 1C, after the photoresist pattern is removed, impurity-doping using n.sup.- -type impurities (impurities for forming n.sup.- semiconductor regions) is performed on the entire surface to form LDD regions 10L in the undoped region of the active layer 10 of the pixel electrode TFT. Conventionally, n.sup.- -type impurities of 10.sup.15-18 /cm.sup.3 are doped. The source and drain regions 10S, 10D for the pixel TFT and the source and drain regions 20S, 20D for the n-type circuit TFT, as heavily doped with impurities, are not significantly affected by this light n.sup.- -type impurity-doping. Both sides of channel region 20'C in the active layer 20' for the p-type circuit TFT are lightly doped with n.sup.- impurities to form lightly doped regions 20'L.
Referring to FIG. 1D, a photoresist layer is formed on the entire surface, and selective exposure and development are carried out to form a photoresist pattern PR covering the entire surface of the active layers 10 and 20.
Impurity-doping using p.sup.+ -type impurities (impurities for forming p.sup.+ semiconductor regions) is then performed on the entire surface to form source and drain regions 20'S and 20'D in the active layer 20' of the p-type circuit TFT. Conventionally, p.sup.+ -type impurities of about 10.sup.19-21 /cm.sup.3 are doped. The photoresist pattern PR formed over the active layers 10 and 20 functions as a mask for blocking the p.sup.+ -type impurities. As a result, the source and drain regions 20'S and 20'D are formed only in the active layer 20' of the p-type circuit TFT. These regions 20'S and 20'D are in contact with the respective sides of the channel region 20C'. This type of doping: e.g., n.sup.- -type impurities of about 10.sup.15-18 /cm.sup.3 doped and p.sup.+ -type impurities of about 10.sup.19-21 /cm.sup.3 subsequently doped into the same region of the active layer, is termed "counter doping method." The lightly doped n.sup.- -type impurity region can be doped with p.sup.+ -type impurities so that the source and drain regions for the p-type circuit TFT are formed in the active layer with p.sup.+ impurities dominant. The impurity regions formed in the respective active layers are activated by annealing the entire substrate by means of heat energy, such as laser irradiation.
Referring to FIG. 1E, an insulating interlayer 110 is formed by depositing an insulating material on the entire surface, using a conventional PECVD method. The insulating interlayer 110 is then pattern-etched by a photolithographic process to form contact holes exposing the respective source and drain regions of the pixel TFT, n-type circuit TFT, and the p-type circuit TFT.
A metal layer including a metallic material such as aluminum, chrome, or the like, is formed over the entire surface and is pattern-etched by a photolithographic process to form metal patterns that are connected to the respective impurity regions. The metal patterns for circuit TFT complete a CMOS structure with the n-type circuit TFT and the p-type circuit TFT. The metal patterns include source and drain electrodes 13S and 13D connected to the source and drain regions 10S and 10D of the pixel TFT; a first metal pattern 23-1 connected to the source region 20S of the n-type circuit TFT; a second metal pattern 23-2 connected to the source region 20'S of the p-type circuit TFT; and a third metal pattern 23-3 connecting the drain region 20D of the n-type circuit TFT to the drain region 20'D of the p-type circuit TFT.
Referring to FIG. 1F, a protective layer 120 is formed by depositing an insulating layer on the entire surface. The protective layer is pattern-etched by a photolithographic process to form a contact hole exposing the drain electrode 13D of the pixel TFT. Then, a transparent conductive layer is formed on the entire surface and pattern-etched by a photolithographic process to form a pixel electrode 15 connected to the drain electrode 13D of the pixel TFT.
In the conventional thin film transistor above, the source and drain regions are formed by doping impurities having high energies into the active layer and silicon layer, and the LDD regions are also formed in the same manner. The doped impurities, having high energies, repeatedly collide with silicon atoms in the silicon layer, and stop at predetermined positions. This produces structural defects around the impurities' paths. In other words, the impurities doped into the active layer destroy the crystal structure of the silicon layer, forming many trap states in the silicon layer. These trap states capture and/or scatter carriers fed by the doped impurities, and interfere with carriers' movement. As a result, the switching characteristic of the resultant TFT may become poor and the reliability of the thin film transistor may be degraded.